1. Field of the Invention
The present invention relates to a method for fabricating a nonvolatile ferroelectric memory.
2. Background of the Related Art
FeRAM(Ferroelectric Random Access Memory) of a ferroelectric film has been widely studied as a memory which can replace nonvolatile memories, such as current flash memory, because, in general, the FeRAM not only has advantages of a fast writing speed, a low voltage driving, and a low power consumption, but also has a nonvolatile characteristic. In the current ferroelectric memories, there are ones with pairs of transistor and capacitor(1 transistor/1 capacitor type, 2 transistor/2 capacitor type), and ones with the ferroelectric film on a gate to form one transistor(1 transistor type). Researches for the ferroelectric memory is mostly focused on the 1 transistor/1 capacitor type.
In the meantime, recently a new type of SWL(Split Word Line) ferroelectric memory has been suggested, of which structure is as follows. FIG. 1A illustrates a circuit of a related art ferroelectric memory cell, and FIG. 1B illustrates a circuit of a related art SWL ferroelectric memory cell.
Referring to FIGS. 1A and 1B, though the SWL ferroelectric memory has no plateline of the related art ferroelectric memory, the SWL ferroelectric memory has the SWL adapted to serve as a wordline as well as a plateline of an adjacent cell. That is, different from the related art ferroelectric memory in which the platelines are electrically connected to a common line, since the SWL, ferroelectric memory has the SWL, serving as the plateline, not connected in common, the SWL feitoelectric memory is operative at a fast speed, and prevents degradation of unselected cells during writing/reading operation of selected cells. As shown in FIG. 1B, the SWL ferroelectric memory has the wordline connected to a lower electrode of the capacitor in an adjacent cell, to form the SW1. wordline. Therefore, it is favorable that the ferroelectric capacitor is formed on the wordline for fabricating a ferroelectric memory with a high device packing density. In this instance, the wordline and the lower electrode is electrically connected either directly by a conducting barrier formed between the wordline and the lower electrode, or by a metal interconnection in a contact hole formed between the lower electrode and the wordline.
FIG. 2 illustrates a section of the SWL ferroelectric memory, of which fabrication process is similar to a fabrication process of the related art ferroelectric memory.
First, a gate oxide(SiO.sub.2) layer and a polysilicon(Poly-Si) layer are formed over a substrate having a field oxide formed therein, and patterned, to form a wordline, and source/drain regions are formed on both sides of the wordline. Then, after an insulating layer is formed on an entire surface, a lower electrode, a ferroelectric layer, and an upper electrode are formed in succession on the insulating layer on the wordline, and patterned, to form a ferroelectric capacitor.
However, the related art method for fabricating the SWL ferroelectric memory has the following problem. The alignment allowance required between the wordline and the ferroelectric memory is not favorable for fabrication of a memory with a high device packing density and requires many fabrication process steps.